IEEE

OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design

Abstract: OpenRTLSet 1 introduces the largest fully open-source dataset for hardware design, offering over 127,000 diverse Verilog code samples to the research community and industry. Our dataset ...
GitHub

A VS Code extension bundling all the things I want in a System Verilog IDE.

The language server provides a couple of features from the Verible SystemVerilog productivity suite right in the editor.
IEEE

V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation

Abstract: This paper introduces a streamlined SystemVerilog & Verilog-to-Verilog-A (V2Va +) translation tool that automates the conversion of synthesizable SystemVerilog and Verilog code into ...
GitHub

ArvinDelavari/Digital-Circuits-Verilog

This repository includes some sample digital circuits scripted in Verilog HDL. Purpose of this repository is to maintain some useful and common modules used in digital design and CPU designed ...