Nature

Low Power SRAM Design and Technology

Low power Static Random-Access Memory (SRAM) design remains at the forefront of research in modern electronics due to its critical role in minimising energy consumption while maintaining high ...
Electronic Design

SRAM Deliver Higher Density Than 6T Solutions

Toted as the industry's highest density SRAM devices, the 72 Mb no bus latency (NoBL) burst SRAM family employ a patented one-transistor enhanced SRAM technology to achieve the same speed, four times ...
EDN

Low Power SRAM Design [Cadence ICFB, Synopsys DC, 0.12μmCMOS, Hspice]

Designed an 8-Kbit SRAM using sleep transistors to reduce power dissipation. 130nm technology is used to design SRAM cells and HSPICE simulations are used to determine the optimal number and sizes of ...
EDN

256 kB Advanced Low Power SRAM

The R1LP5256E is an advanced low power SRAM featuring single power supply with small stand-by current. It has no clocks and refresh, and offers 3-state outputs with easy memory expansion.The R1LP5256E ...