Semiconductor Engineering

Power Reduction At RTL: Data Gating Adders And Multipliers

In our previous blog, “Low Power Paradox”, we discussed the implications of the move to FinFET technology. Dynamic power is dominant in finFET designs. Several techniques are available to reduce ...
EDN

Top-down DSP design for FPGAs

Digital filtering of non-real-time signals has been performed for decades. The increased performance in today's silicon allows for these calculations to be accomplished in real-time, if the right ...
EDN

Filter banks, part 2: Optimization and synthesis

Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample ...
Linux Journal

Xilinx FPGA Design Tools for Linux

A field programmable gate array (FPGA) is a user-programmable piece of silicon constructed in very large-scale integration (VLSI) technology. The VLSI transistor-level detail is absolutely predefined ...
Design-Reuse

Building an FPGA FIFO without using logic recourses

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...