In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize ...

TSMC’s roadmap announcement for their 28 nm node yesterday has stirred considerable controversy already. The issue is the company’s decision to divide their process development into two tracks: one to ...

A dc-blocking capacitor, which youcommonly apply in series with each data wire in a differential link, can servemany purposes. It can, for example, shift the average dc-bias level of thesignal to ...

Because of their high ESL compared to ceramic, tantalum capacitors are not the optimum choice for high frequency decoupling. Paralleling tantalum capacitors for bulk capacitance and ceramic for high ...

Although SPICE can be a powerful tool, there are pitfalls in relying solely on simulation. To avoid unpleasant surprises, it's imperative that a SPICE simulation be anchored to a detailed ...