Design-Reuse

Fifo in vlsi IP Listing

The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 APB System Interconnect Fabric to an I2C ... I2C ...
Design-Reuse

Lattice Fifo IP Listing

The USB 2.0 Device with FIFO Interface (USB20HF) IP Core supports ULPI interface with Bulk IN and Bulk OUT endpoints. The core supports three preconfigured endpoints Control, Bulk IN, and Bulk ... The ...
EDN

Dual-mode Soft IP core supports UART and FIFO operation

Digital Core Design has announced its D16950 soft IP core, featuring functional compatibility with the OX16C950 and an ability to support serial transmission in UART and FIFO modes. Building on its ...
Electronics Weekly

SPI FIFO can configure serial clock signal

Digital Core Design, the Poland-based IP core design house, has developed the DSPI_FIFO, a fully configurable SPI master/slave device, which allows the SoC designer to configure polarity and phase of ...
EDN

FPGA PCI core supports up to six FIFO connections with no data loss

Mountain View, Calif. — Actel Corp. has developed a versatile field-programmable gate array (FPGA) PCI core called CorePCIF that connects memory, FIFO and processor subsystem resources through the PCI ...