Shutting down inactive circuitry can save substantial power; however, this kind of power management assumes there is an actively managing “brain” (typically a microcontroller) that knows when to turn ...

David Albean, Thomson Consumer Electronics, Indianapolis, INA simple enhancement of an earlier Design Idea (“Delay line implements clock doubler”,EDN, July 18, 1996, pg 102) implements a variable-duty ...

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, ...

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, ...

A free-running generator built on the standard configuration of the 555 timer can't provide a duty cycle of exactly 50%. That's a well-known fact. Fortunately, there are several ways to get around ...