Asynchronous, or clockless, logic–an alternative to standard digital circuits that avoids many of their problems–is beginning to look attractive for embedded designs in consumer electronics and mobile ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

At 0.18 micron and below, handling crosstalk becomes a significant design challenge. Historically safe and pervasive design techniques may now increase crosstalk, and must be reviewed for suitability.

CMOS is, and will continue to be, the work-horse process technology of the semi-conductor industry. But designers of large devices, of complex SoCs and of devices using multiple IP elements are ...

Earlier designs were smaller, less complex, and had simpler clocking. A few years back, verification was much easier and clock modeling was not such a big concern. With the drastic increase in the use ...

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with ...

You only need to validate one core of a CMP design. So if that core is simpler, validation is easier. And you have to worry about the rest of the logic no matter what your core design is. You dont get ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.