Cupertino, Calif. How do you design a 10-million-gate chip on a tight schedule? Not one gate at a time. Simon Bloch is president and CEO of Aristo Technology Inc., Cupertino, Calif. The recent winner ...

Properly designing the gate drive circuit for high-voltage MOSFETs is essential to ensure proper performance from the MOSFET one desires. Far too often, engineers find themselves having difficulty in ...

The digital toolkit consists of six modules, including four all-new applications and substantially upgraded versions of well-known Gates digital tools, Design IQ and Design Flex Pro. Among the all-new ...

A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2 ...

In IP based SoC design era, it is highly desirable to have near-accurate gate count (area) estimates upfront during micro-architecture phase of IP development. This gate count estimate will enable SoC ...